The Cache InjectionKofetch Architecture: Initial Performance Evaluation

One of t?ie major problems in. a n,umber of SM (Shared Memory) and DSM (Distributed Shared Memory) applications is the overall cost of read misses in conditions when.: (a) system latencies are relatively large, and (b) a shared data item is read relatively few times b.y each of the processors in the system; modern SM and DSM systerns are typically based on. off-the-shelf microprocessors which do not include an.y support for the described problem. Con.sequently, the major goal of our research is to come up with a new con.cept to be incorporated into the n.ext generation microprocessors, so they can become more eficient in the sense described above. Existing 64bit processors support only data prefetching (PF) as a method to fight against negative effects of the described problem. Our research introduces a mew concept referred to as cache injection (Cl), as well as the related cache injectionkofetch architecture (CICA). Initial performance evaluation is pegormed using a simulation methodology based on the set of synthetic benchmarks of interest for the research sponsor.